1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an output driver of a semiconductor memory device.
2. Description of the Related Art
The bit organization, i.e., the number of bits of data that are output simultaneously, of a semiconductor memory device such as an asynchronous dynamic random access memory (ASDRAM), RAMBUS DRAM, is determined by the chip design. In other words, the bit organization is selected from among various bit organizations, such as X4, X8, and X16, in designing the chip, and internal circuits are designed according to the selected bit organization
In contrast, in the case of a double data rate (DDR) synchronous DRAM (SDRAM), after several different bit organizations are installed in one chip in the chip design, and one bit organization is later set by bonding wire connection(s) in the manufacturing process. In other words, a bit organization of X4, X8, or X16 is selected according to a bonding wire connection state.
However, one of issues arising when several bit organizations are installed in one chip in a DDR SDRAM is that the slew rate of a signal output from a data output driver depends on the bit configuration. The slew rate generally indicates the amount of change in a voltage of a signal per unit time and is often referred to as a rise time or a fall time.
FIG. 1 illustrates a configuration of a data output driver in a DDR SDRAM. As described above, in the case of a DDR SDRAM, several bit organizations are installed in one chip in the chip design. Therefore, all bit organizations, such as X4, X8, X16, and the like should be considered in a designing process, and thus sixteen data output drivers 1 through 16 are divided into 6 or 7 groups in which each group includes 2 or 3 data output drivers as shown in FIG. 1, and a power line, i.e. a supply voltage line VDDQ, and a ground voltage line VSSQ are connected to each group.
In this case, all of the sixteen data output drivers 1 through 16 are used in a X16 product, while only 4 data output drivers are used in a X4 product (when the data output drivers 1 through 16 are grouped into 4 groups). Thus, the X4 product has VDDQ/VSSQ power characteristics that are superior to that of the X16 product. As a result, the slew rate of a signal output from a data output driver in the X4 product is greater than in the X16 product. Namely, in general, the slew rate of a signal output from a data output driver in a X8 product is greater than in the X16 product and the slew rate in the X4 product is greater than in the X8 product.
However, during the designing process, as mentioned above, several bit organizations are optionally designed in one chip and the slew rate of a data output driver is fit into one of the bit organizations. For this reason, in the remaining bit organizations, the slew rate of a data output driver falls outside the optimum point. In other words, when several bit organizations are installed in one chip, the slew rate of a signal output from a data output driver changes with a bit organization.
Accordingly, it would be desirable to provide a data output driver of a semiconductor memory device which minimizes a difference in slew rate of an output signal according to a selected bit organization.
According to one aspect of the present invention, a data output driver of a semiconductor memory device, which drives an output terminal, comprises: a pull-up driver, which pulls up the output terminal; and a pull-down driver, which pulls down the output terminal, wherein current driving capabilities of at least one of the pull-up driver and/or the pull-down driver are changed in response to a selected bit organization of the semiconductor memory device.
The pull-up driver may include a pull-up transistor, which is controlled by a pull-up driving signal and is connected between a supply voltage and the output terminal; and a logic gate, which inverts data and generates the pull-up driving signal, wherein a current driving capability of the logic gate is changed in response to the selected bit organization.
The pull-down driver may include a pull-down transistor, which is controlled by a pull-down driving signal and is connected between the output terminal and a ground voltage; and a logic gate, which inverts data and generates the pull-down driving signal, wherein a current driving capability of the logic gate is changed in response to the selected bit organization.